RESUME




Objective : Seeking a challenging and responsible position in the field of ASIC designing/testing, verification.

Personal:

Name : S Gane Naik.

Date of Birth : 01/05/1975.

Address for Communication : 174B, 5th Cross-B,

First floor, Sundar Nagar,

Gokula P.O,

Bangalore 560 054,

Karnataka state,

India

Email:  [email protected]

Passport Number : A6808501   Issued at Bangalore.

Educational qualifications:

1998 – M.Tech in Communication Systems from Indian Institute of Technology (IIT), Madras.

1996 – B.Tech in Electronics & Communication from Regional Engineering College (REC), Warangal.

Skills:

ASIC/Logic Design HDL Modeling


EDA Tools :
                                 Logic Simulators : Verilog-XL (Cadence), VCS (Synopsys), V-System (Model Technology)
                                 Login Synthesizers : Design Compiler (Synopsys), Galileo for FPGA’s (Examplar)

Static Timing Analysis : Prime Time

Hardware Descriptive Language : Verilog, VHDL.

High Level Programming : C, Pascal, Matlab , Unix shell programming.

Operating Systems : UNIX, Sun SOLARIS, WIN-NT.

Hardware Platforms : Sun UltraSparc-60, Pentium Pro.
 
 
 
 
 
 
 
 

Area of interest : Digital Signal Processing  , Computer networks , HDL Modeling
 

Professional Training in Japan :

One month training on the following,

  1. Verilog-HDL & Synopsys Design Flow
  2. Prime Time
  3. Synopsys Test Compiler/Test Gen
  4. JTAG
  5. ASPEC Design Verifier (ADVER) Tool
ADVER is a multi-function front and back-end engineering utility program for reading netlists,

Calculation of delays, translating netlists to different formats, checking logic design rules, generating

Reports and more. ADVER generates output delay files (SDF) for back-annotation and SPICE files for

Layout vs schematic check.
 
 

Professional experience:

Projects associated with Central Research Laboratory (CRL) of Bharat Electronics Ltd (a Government of India Defence Undertaking) as Member Research Staff from Feb '98 to Oct '98.

1. Design and implementation of 512-point radix 8 pipelined Fast Fourier Transform(FFT )processor

targeted on Xilinx FPGA.

Abstract: This project uses an architecture which consists of 8-point FFT processor, two memory blocks and a control circuit. It uses a single point 8-point processor in time shared manner and takes advantage of the pipeline operation of the 8-point FFT processor. The control circuit lets the FFT processor to access several memories simultaneously.

Personal Contribution : Was involved in the design, coding and simulation of the basic 8-point FFT block and control circuit. Gate count of the design was 21k gates.
 
 
 
 

skilllls Acquired :              Got acquainted with VHDL programming and Xilinx/XACT tool for targeting on Xilinx  4000 series FPGA’s.

Team size : 2
 
 
 
 
 
 

2. With SANYO LSI Technology India Pvt Ltd as Design Engineer since Nov '98 .

Projects :

  1. Design and implementation of Memory Control Unit(MCU) , which is used in the display controller chip. This chip is used in car navigation system.

    2.  

     

    Abstract: MCU, generates memory(16MB EDO/SDRAM) control signals such as write, read and refresh. It consist of

    4 basic blocks (1) Address Generating Unit(AGU), which generates address for reading & writing to & from DRAM. (2) Access Time Controller, controls the DRAM read, write and refresh timings. (3) Write Read Controller, controls the programmable registers, it also generates refresh signals to the DRAM. (4) Buffer Control Unit, controls the display and input buffers. Display buffer is configured in 2 stages, one for displaying and another for reading from DRAM.

    Personal Contribution : Write Read Controller, Buffer control Unit and 16MB EDO/SDRAM modeling.

    Skills Acquired : Got acquainted with Verilog modeling/Coding, Simulation and Synthesis using scripts.

    Team size : 2.

  2. Design and implementation of 8K(8192) complex point Fast Fourier Transform(FFT) ,which is used in the OFDM demodulator for Digital Broadcasting.
Abstract: This is implemented using Radix 4 and Radix 2 Cooley & Tukey algorithm. The architecture consists of an optimized arithmetic, realized with several complex adders and multipliers, to compute the FFT butterfly and multiplication by the twiddle factors. A ROM to store twiddle factors, N-word RAM to store the intermediate results, a N-word input buffer to store the input samples and a control unit for address generation and selection of any size FFT ranging from 16 point FFT to 8192(8K) point FFT.

Personal Contribution : Involved in the complete design and implementation. Presently working on this.

Skills Acquired : Strengthened the skills on Verilog coding, Simulation and Synthesis.

Team size : 2
 
 

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